SN74LS166AD

Регистр сдвига, семейство LS, Параллельный в Последовательный, Последовательный в Последовательный.

The SN74LS166AD is a 8-bit parallel-load serial-out Shift Register compatible with most other TTL logic families. This parallel-in or serial-in, serial-out shift register has a complexity of 77 equivalent gates on a monolithic chip. It features gated clock inputs and an overriding clear input. The parallel-in or serial-in modes are established by the shift/load input. When high, this input enables the serial data input and couples the eight flip-flops for serial shifting with each clock pulse. When low, the parallel (broadside) data inputs are enabled and synchronous loading occurs on the next clock pulse. During parallel loading, serial data flow is inhibited. clocking is accomplished on the low-to-high-level edge of the clock pulse through a two-input positive NOR gate permitting one input to be used as a clock-enable or clock-inhibit function. Holding either of the clock inputs high inhibits clocking, holding either low enables the other clock input.