CDCLVD1213RGTT
- ΠΠ°Π»ΠΈΡΠΈΠ΅: ΠΠΎΠ΄ Π·Π°ΠΊΠ°Π· 3-4 Π½Π΅Π΄Π΅Π»ΠΈ
1 929 β½
CLOCK BUFFER, 800MHZ, QFN-16.
The CDCLVD1213RGTT is a Clock Buffer distributes an input clock to 4 pairs of differential LVDS clock outputs with low additive jitter for clock distribution. The input can either be LVDS, LVPECL or CML. The CDCLVD1213 contains a high performance divider for one output (QD) which can divide the input clock signal by a factor of 1, 2 or 4. The CDCLVD1213 is specifically designed for driving 50R transmission lines. The part supports a fail-safe function. The device incorporates an input hysteresis which prevents random oscillation of the outputs in the absence of an input signal. The device operates in 2.5V supply environment and is characterized from -40 to 85Β°C (ambient temperature).
Π₯Π°ΡΠ°ΠΊΡΠ΅ΡΠΈΡΡΠΈΠΊΠΈ | |
SVHC (ΠΡΠΎΠ±ΠΎ ΠΠΏΠ°ΡΠ½ΡΠ΅ ΠΠ΅ΡΠ΅ΡΡΠ²Π°) | No SVHC (15-Jun-2015) |
ΠΠΎΠ»ΠΈΡΠ΅ΡΡΠ²ΠΎ ΠΡΠ²ΠΎΠ΄ΠΎΠ² | 16Π²ΡΠ²ΠΎΠ΄(-ΠΎΠ²) |
ΠΠΎΠ»ΠΈΡΠ΅ΡΡΠ²ΠΎ ΠΡΡ ΠΎΠ΄ΠΎΠ² | 4Π²ΡΡ ΠΎΠ΄(-ΠΎΠ²) |
ΠΠΈΠ½ΠΈΡ ΠΡΠΎΠ΄ΡΠΊΡΠΈΠΈ | - |
ΠΠ°ΠΊΡΠΈΠΌΠ°Π»ΡΠ½Π°Ρ Π Π°Π±ΠΎΡΠ°Ρ Π’Π΅ΠΌΠΏΠ΅ΡΠ°ΡΡΡΠ° | 85Β°C |
ΠΠ°ΠΊΡΠΈΠΌΠ°Π»ΡΠ½ΠΎΠ΅ ΠΠ°ΠΏΡΡΠΆΠ΅Π½ΠΈΠ΅ ΠΠΈΡΠ°Π½ΠΈΡ | 2.625Π |
ΠΠΈΠ½ΠΈΠΌΠ°Π»ΡΠ½Π°Ρ Π Π°Π±ΠΎΡΠ°Ρ Π’Π΅ΠΌΠΏΠ΅ΡΠ°ΡΡΡΠ° | -40Β°C |
ΠΠΈΠ½ΠΈΠΌΠ°Π»ΡΠ½ΠΎΠ΅ ΠΠ°ΠΏΡΡΠΆΠ΅Π½ΠΈΠ΅ ΠΠΈΡΠ°Π½ΠΈΡ | 2.375Π |
Π‘ΡΠΈΠ»Ρ ΠΠΎΡΠΏΡΡΠ° ΠΠ‘ Π’Π°ΠΊΡΠΎΠ²ΠΎΠ³ΠΎ ΠΠ΅Π½Π΅ΡΠ°ΡΠΎΡΠ° | QFN |
Π’ΠΈΠΏ ΠΠΈΠΊΡΠΎΡΡ Π΅ΠΌΡ Π’Π°ΠΉΠΌΠ΅ΡΠ° | ΠΡΡΠ΅Ρ Π’Π°ΠΊΡΠΎΠ²ΡΡ Π‘ΠΈΠ³Π½Π°Π»ΠΎΠ² |
Π£ΠΏΠ°ΠΊΠΎΠ²ΠΊΠ° | ΠΠΎΡΡΡΡΠ½ΠΎ |
Π£ΡΠΎΠ²Π΅Π½Ρ Π§ΡΠ²ΡΡΠ²ΠΈΡΠ΅Π»ΡΠ½ΠΎΡΡΠΈ ΠΊ ΠΠ»Π°ΠΆΠ½ΠΎΡΡΠΈ (MSL) | MSL 2 - 1 Π³ΠΎΠ΄ |
Π§Π°ΡΡΠΎΡΠ° | 800ΠΠΡ |