MC100LVEP111FAG

IC, SM, LOGIC, ECL, CLOCK GEN.

The MC100LVEP111FAG is a 2:1:10 low skew Differential Driver designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The PECL input signals can be either differential or single-ended (if the VBB output is used). HSTL inputs can be used when the LVEP111 is operating under PECL conditions. The LVEP111 specifically guarantees low output-to-output skew. Optimal design, layout and processing minimize skew within a device and from device to device. To ensure tightest skew, both sides of differential outputs identically terminate into 50 even if only one output is being used. If an output pair is unused, both outputs may be left open (unterminated) without affecting skew. It can be operated from a positive VCC supply in PECL mode. This allows the LVEP111 to be used for high performance clock distribution in 3.3 or 2.5V systems. Single-ended CLK input operation is limited to a VCC>=3V in PECL mode or VEE -3V in NECL mode when using VBB.