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TEXAS INSTRUMENTS

IC, DECODER/DEMUX, 74LC138.The SN74LS138D is a 3-to-8 Decoder/Demultiplexer designed to be used in high-performance memory decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, these decoders can be used to minimize the effects of sys..
75 β‚½
DECODER/DEMULTIPLEXER, 3:8, SOIC-16.The SN74LS138DR is a 3-to-8 Decoder/Demultiplexer designed to be used in high-performance memory decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, it can be used to minimize the effects of syste..
69 β‚½
LOGIC, 3-8 LINE DECODER/DEMUX, 16DIP.The SN74LS138N is a 3-line to 8-line Decoder/Demultiplexer, Schottky-clamped TTL MSI circuit is designed to be used in high-performance memory decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, ..
72 β‚½
IC, SM, LOGIC, 74LS, DECODER...
72 β‚½
IC, DECODER/DEMUX, 74LS139.The SN74LS139AN is a Dual 2-line to 4-line Decoder/Demultiplexer, Schottky-clamped TTL MSI circuit, designed to be used in high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, these ..
78 β‚½
IC, DECODER/DRIVER, 74LC145, SOIC16.The SN74LS145D is a BCD-to-decimal Decoder or Driver with eight inverters and ten 4-input NAND gates. The inverters are connected in pairs to make BCD input date available for decoding by the NAND gates. Full decoding of valid BCD input logic ensures that all outp..
98 β‚½
DECODER, BCD-DECIMAL, SOIC-16.The SN74LS145DR is a BCD-to-decimal Decoder/Driver consists of eight inverters and ten 4-input NAND gates. The inverters are connected in pairs to make BCD input date available for decoding by the NAND gates. Full decoding of valid BCD input logic ensures that all outpu..
115 β‚½
IC, DECODER/DRIVER.The SN74LS145N is a BCD-to-decimal Decoder/Driver consists of eight inverters and ten four-input NAND gates. The inverters are connected in pairs to make BCD input date available for decoding by the NAND gates. Full decoding of valid BCD input logic ensures that all outputs remain..
107 β‚½
LOGIC, PRIORITY ENCODER 8-3L, 16SOIC...
272 β‚½
IC, PRIORITY ENCODER...
262 β‚½
Π˜Π½Π²Π΅Ρ€Ρ‚ΠΎΡ€, Ρ‚Ρ€ΠΈΠ³Π³Π΅Ρ€ Π¨ΠΌΠΈΡ‚Ρ‚Π°, 1 Π²Ρ…ΠΎΠ΄, 8мА, 4.75Π’ Π΄ΠΎ 5.25Π’, SOIC-14...
88 β‚½
IC, HEX INVERTER, SCHMITT TRIGGER SOIC14...
113 β‚½
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