CDCE706PWG4

CLOCK GENPROG 3PLL 300MHZ, SMD, 706.

The CDCE706PWG4 is a 3-PLL Programmable Clock Synthesizer/Multiplier/Divider despite its small physical outlines, it is very flexible. It has the capability to produce an almost independent output frequency from a given input frequency. The input frequency can be derived from a LVCMOS, differential input clock or a single crystal. The appropriate input waveform can be selected via the SMBus data interface controller. To achieve an independent output frequency the reference divider M and the feedback divider N for each PLL can be set to values from 1 up to 511 for the M-divider and from 1 up to 4095 for the N-divider. The PLL-VCO (voltage controlled oscillator) frequency than is routed to the free programmable output switching matrix to any of the six outputs. The switching matrix includes an additional 7-bit post-divider (1-to-127) and an inverting logic for each output. The deep M/N divider ratio allows the generation of zero ppm clocks from any reference input frequency (27MHz).