SN65LVDS93ADGG

SerDes, Параллельно-последовательный Преобразователь / Последовательно-параллельный Преобразователь.

The SN65LVDS93ADGG is a LVDS SerDes (serializer/deserializer) FlatLink™ Transmitter contains four 7-bit parallel load serial-out shift registers, a 7 x clock synthesizer and five low-voltage differential signalling (LVDS) drivers in a single integrated circuit. These functions allow synchronous transmission of 28 bits of single-ended LVTTL data over five balanced-pair conductors for receipt by a compatible receiver, such as the SN65LVDS94 (SLLS928). When transmitting, data bits D0 through D27 are each loaded into registers upon the edge of the input clock signal (CLKIN). The rising or falling edge of the clock can be selected through the clock select (CLKSEL) pin. The frequency of CLKIN is multiplied seven times and then used to serially unload the data registers in 7-bit slices. The four serial streams and a phase-locked clock (CLKOUT) are then output to LVDS output drivers. The frequency of CLKOUT is the same as the input clock, CLKIN.