CDCLVD1216RGZT

CLOCK BUFFER, 800MHZ, VQFN-48.

The CDCLVD1216RGZT is a Clock Buffer distributes one of two selectable clock inputs (IN0, IN1) to 16 pairs of differential LVDS clock outputs (OUT0, OUT15) with minimum skew for clock distribution. It can accept two clock sources into an input multiplexer. The inputs can either be LVDS, LVPECL or LVCMOS. It is specifically designed for driving 50R transmission lines. If driving the inputs in single ended mode, the appropriate bias voltage (VAC_REF) should be applied to the unused negative input pin. The IN_SEL pin selects the input which is routed to the outputs. If this pin is left open it disables the outputs (static). The part supports a fail-safe function. It incorporates an input hysteresis, which prevents random oscillation of the outputs in absence of an input signal.