CDCLVP2102RGTT

BUFFER, DUAL, 1:2, LVPECL, 16QFN.

The CDCLVP2102RGTT is a highly versatile low additive Jitter Buffer can generate four copies of LVPECL clock outputs from two LVPECL, LVDS or LVCMOS inputs for a variety of communication applications. It has a maximum clock frequency up to 2GHz. Each buffer block consists of one input that feeds two LVPECL outputs. The overall additive jitter performance is less than 0.1ps, RMS from 10kHz to 20MHz and overall output skew is as low as 10ps, making the device a perfect choice for use in demanding applications. The CDCLVP2102 clock buffer distributes two clock inputs (IN0, IN1) to four pairs of differential LVPECL clock outputs (OUT0, OUT3) with minimum skew for clock distribution. Each buffer block consists of one input that feeds two LVPECL clock outputs. The inputs can be LVPECL, LVDS or LVCMOS/LVTTL. The CDCLVP2102 is specifically designed for driving 50R transmission lines.