
- ΠΠ°Π»ΠΈΡΠΈΠ΅: ΠΠΎΠ΄ Π·Π°ΠΊΠ°Π· 3-4 Π½Π΅Π΄Π΅Π»ΠΈ
D-TYPE LATCH, SMD, SC-70-6, 3.3V, REEL.
The SN74LVC1G373DCKR is a single D Latch designed for 1.65 to 5.5V VCC operation. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers and working registers. While the LE input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs. While the LE input is high, the Q output follows the data (D) input. When LE is taken low, the Q output is latched at the logic level set up at the D input. OE\ does not affect the internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. A buffered OE\ input can be used to place the output in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the output neither loads nor drives the bus lines significantly.
Π₯Π°ΡΠ°ΠΊΡΠ΅ΡΠΈΡΡΠΈΠΊΠΈ | |
SVHC (ΠΡΠΎΠ±ΠΎ ΠΠΏΠ°ΡΠ½ΡΠ΅ ΠΠ΅ΡΠ΅ΡΡΠ²Π°) | No SVHC (15-Jun-2015) |
ΠΡΡ ΠΎΠ΄Π½ΠΎΠΉ Π’ΠΎΠΊ | 32ΠΌΠ |
ΠΠ°Π΄Π΅ΡΠΆΠΊΠ° Π Π°ΡΠΏΡΠΎΡΡΡΠ°Π½Π΅Π½ΠΈΡ | 4Π½Ρ |
ΠΠΎΠ»ΠΈΡΠ΅ΡΡΠ²ΠΎ ΠΠΈΡ | 1Π±ΠΈΡ |
ΠΠΎΠ»ΠΈΡΠ΅ΡΡΠ²ΠΎ ΠΡΠ²ΠΎΠ΄ΠΎΠ² | 6Π²ΡΠ²ΠΎΠ΄(-ΠΎΠ²) |
ΠΠΈΠ½ΠΈΡ ΠΡΠΎΠ΄ΡΠΊΡΠΈΠΈ | - |
ΠΠ°ΠΊΡΠΈΠΌΠ°Π»ΡΠ½Π°Ρ Π Π°Π±ΠΎΡΠ°Ρ Π’Π΅ΠΌΠΏΠ΅ΡΠ°ΡΡΡΠ° | 85Β°C |
ΠΠ°ΠΊΡΠΈΠΌΠ°Π»ΡΠ½ΠΎΠ΅ ΠΠ°ΠΏΡΡΠΆΠ΅Π½ΠΈΠ΅ ΠΠΈΡΠ°Π½ΠΈΡ | 5.5Π |
ΠΠΈΠ½ΠΈΠΌΠ°Π»ΡΠ½Π°Ρ Π Π°Π±ΠΎΡΠ°Ρ Π’Π΅ΠΌΠΏΠ΅ΡΠ°ΡΡΡΠ° | -40Β°C |
ΠΠΈΠ½ΠΈΠΌΠ°Π»ΡΠ½ΠΎΠ΅ ΠΠ°ΠΏΡΡΠΆΠ΅Π½ΠΈΠ΅ ΠΠΈΡΠ°Π½ΠΈΡ | 1.65Π |
Π‘ΡΠΈΠ»Ρ ΠΠΎΡΠΏΡΡΠ° ΠΠΈΠΊΡΠΎΡΡ Π΅ΠΌΡ ΠΠΎΠ³ΠΈΠΊΠΈ | SC-70 |
Π’ΠΈΠΏ ΠΡΡ ΠΎΠ΄Π° ΠΠΈΠΊΡΠΎΡΡ Π΅ΠΌΡ | Π‘ Π’ΡΠ΅ΠΌΡ Π‘ΠΎΡΡΠΎΡΠ½ΠΈΡΠΌΠΈ ΠΠ΅ΠΈΠ½Π²Π΅ΡΡΠΈΡΡΡΡΠΈΠΉ |
Π’ΠΈΠΏ ΠΠ°ΡΠ΅Π»ΠΊΠΈ | D Π’ΠΈΠΏΠ° |
Π£ΠΏΠ°ΠΊΠΎΠ²ΠΊΠ° | ΠΠ΅Π½ΡΠ° ΠΈ ΠΠ°ΡΡΡΠΊΠ°/ΠΠΎΠ±ΠΈΠ½Π° |
Π£ΡΠΎΠ²Π΅Π½Ρ Π§ΡΠ²ΡΡΠ²ΠΈΡΠ΅Π»ΡΠ½ΠΎΡΡΠΈ ΠΊ ΠΠ»Π°ΠΆΠ½ΠΎΡΡΠΈ (MSL) | MSL 1 - ΠΠ΅Π·Π»ΠΈΠΌΠΈΡΠ½ΡΠΉ |