
CD4520BM
- ΠΠ°Π»ΠΈΡΠΈΠ΅: ΠΠΎΠ΄ Π·Π°ΠΊΠ°Π· 3-4 Π½Π΅Π΄Π΅Π»ΠΈ
- ΠΡΡΠΈΠΊΡΠ»: CD4520BM
0 β½
LOGIC, DUAL BIN UP-COUNTER, 16SOIC.
The CD4520BM is a dual CMOS Binary Up-Counter consist of two identical, internally synchronous 4-stage counters. The counter stages are D-type flip-flops having interchangeable clock and enable lines for incrementing on either the positive-going or negative-going transition. For single-unit operation the ENABLE input is maintained high and the counter advances on each positive-going transition of the clock. The counters are cleared by high levels on their RESET lines. The counter can be cascaded in the ripple mode by connecting Q4 to the enable input of the subsequent counter while the clock input of the latter is held low.
| Π₯Π°ΡΠ°ΠΊΡΠ΅ΡΠΈΡΡΠΈΠΊΠΈ | |
| SVHC (ΠΡΠΎΠ±ΠΎ ΠΠΏΠ°ΡΠ½ΡΠ΅ ΠΠ΅ΡΠ΅ΡΡΠ²Π°) | No SVHC (15-Jun-2015) |
| ΠΠΎΠ»ΠΈΡΠ΅ΡΡΠ²ΠΎ ΠΡΠ²ΠΎΠ΄ΠΎΠ² | 16Π²ΡΠ²ΠΎΠ΄(-ΠΎΠ²) |
| ΠΠΈΠ½ΠΈΡ ΠΡΠΎΠ΄ΡΠΊΡΠΈΠΈ | - |
| ΠΠ°ΠΊΡΠΈΠΌΠ°Π»ΡΠ½Π°Ρ Π Π°Π±ΠΎΡΠ°Ρ Π’Π΅ΠΌΠΏΠ΅ΡΠ°ΡΡΡΠ° | 125Β°C |
| ΠΠ°ΠΊΡΠΈΠΌΠ°Π»ΡΠ½ΠΎΠ΅ ΠΠ°ΠΏΡΡΠΆΠ΅Π½ΠΈΠ΅ ΠΠΈΡΠ°Π½ΠΈΡ | 18Π |
| ΠΠ°ΠΊΡΠΈΠΌΠ°Π»ΡΠ½ΡΠΉ Π‘ΡΠ΅Ρ | 15 |
| ΠΠΈΠ½ΠΈΠΌΠ°Π»ΡΠ½Π°Ρ Π Π°Π±ΠΎΡΠ°Ρ Π’Π΅ΠΌΠΏΠ΅ΡΠ°ΡΡΡΠ° | -55Β°C |
| ΠΠΈΠ½ΠΈΠΌΠ°Π»ΡΠ½ΠΎΠ΅ ΠΠ°ΠΏΡΡΠΆΠ΅Π½ΠΈΠ΅ ΠΠΈΡΠ°Π½ΠΈΡ | 3Π |
| Π‘ΡΠΈΠ»Ρ ΠΠΎΡΠΏΡΡΠ° ΠΠΈΠΊΡΠΎΡΡ Π΅ΠΌΡ ΠΠΎΠ³ΠΈΠΊΠΈ | SOIC |
| Π’Π°ΠΊΡΠΎΠ²Π°Ρ Π§Π°ΡΡΠΎΡΠ° | 8ΠΠΡ |
| Π’ΠΈΠΏ Π‘ΡΠ΅ΡΡΠΈΠΊΠ° | ΠΠ²ΠΎΠΈΡΠ½ΡΠΉ, ΠΠ²Π΅ΡΡ |
| Π£ΠΏΠ°ΠΊΠΎΠ²ΠΊΠ° | ΠΠΎΡΡΡΡΠ½ΠΎ |
| Π£ΡΠΎΠ²Π΅Π½Ρ Π§ΡΠ²ΡΡΠ²ΠΈΡΠ΅Π»ΡΠ½ΠΎΡΡΠΈ ΠΊ ΠΠ»Π°ΠΆΠ½ΠΎΡΡΠΈ (MSL) | MSL 1 - ΠΠ΅Π·Π»ΠΈΠΌΠΈΡΠ½ΡΠΉ |