
- ΠΠ°Π»ΠΈΡΠΈΠ΅: ΠΠΎΠ΄ Π·Π°ΠΊΠ°Π· 3-4 Π½Π΅Π΄Π΅Π»ΠΈ
LATCH, D-TYPE, TRANSPARENT, 48TSSOP.
The SN74LVCH16373ADGGR is a 16-bit transparent D-Type Latch with 3-state outputs. It is designed for 1.65 to 3.6V VCC operation. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers and working registers. It can be used as two 8-bit latches or one 16-bit latch. When the LE input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D inputs. A buffered OE\ input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pull-up components. OE\ does not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
| Π₯Π°ΡΠ°ΠΊΡΠ΅ΡΠΈΡΡΠΈΠΊΠΈ | |
| SVHC (ΠΡΠΎΠ±ΠΎ ΠΠΏΠ°ΡΠ½ΡΠ΅ ΠΠ΅ΡΠ΅ΡΡΠ²Π°) | No SVHC (15-Jun-2015) |
| ΠΡΡ ΠΎΠ΄Π½ΠΎΠΉ Π’ΠΎΠΊ | 24ΠΌΠ |
| ΠΠ°Π΄Π΅ΡΠΆΠΊΠ° Π Π°ΡΠΏΡΠΎΡΡΡΠ°Π½Π΅Π½ΠΈΡ | 4.2Π½Ρ |
| ΠΠΎΠ»ΠΈΡΠ΅ΡΡΠ²ΠΎ ΠΠΈΡ | 16Π±ΠΈΡ |
| ΠΠΎΠ»ΠΈΡΠ΅ΡΡΠ²ΠΎ ΠΡΠ²ΠΎΠ΄ΠΎΠ² | 48Π²ΡΠ²ΠΎΠ΄(-ΠΎΠ²) |
| ΠΠΈΠ½ΠΈΡ ΠΡΠΎΠ΄ΡΠΊΡΠΈΠΈ | - |
| ΠΠ°ΠΊΡΠΈΠΌΠ°Π»ΡΠ½Π°Ρ Π Π°Π±ΠΎΡΠ°Ρ Π’Π΅ΠΌΠΏΠ΅ΡΠ°ΡΡΡΠ° | 85Β°C |
| ΠΠ°ΠΊΡΠΈΠΌΠ°Π»ΡΠ½ΠΎΠ΅ ΠΠ°ΠΏΡΡΠΆΠ΅Π½ΠΈΠ΅ ΠΠΈΡΠ°Π½ΠΈΡ | 3.6Π |
| ΠΠΈΠ½ΠΈΠΌΠ°Π»ΡΠ½Π°Ρ Π Π°Π±ΠΎΡΠ°Ρ Π’Π΅ΠΌΠΏΠ΅ΡΠ°ΡΡΡΠ° | -40Β°C |
| ΠΠΈΠ½ΠΈΠΌΠ°Π»ΡΠ½ΠΎΠ΅ ΠΠ°ΠΏΡΡΠΆΠ΅Π½ΠΈΠ΅ ΠΠΈΡΠ°Π½ΠΈΡ | 1.65Π |
| Π‘ΡΠΈΠ»Ρ ΠΠΎΡΠΏΡΡΠ° ΠΠΈΠΊΡΠΎΡΡ Π΅ΠΌΡ ΠΠΎΠ³ΠΈΠΊΠΈ | TSSOP |
| Π’ΠΈΠΏ ΠΡΡ ΠΎΠ΄Π° ΠΠΈΠΊΡΠΎΡΡ Π΅ΠΌΡ | Π‘ Π’ΡΠ΅ΠΌΡ Π‘ΠΎΡΡΠΎΡΠ½ΠΈΡΠΌΠΈ |
| Π’ΠΈΠΏ ΠΠ°ΡΠ΅Π»ΠΊΠΈ | ΠΡΠΎΠ·ΡΠ°ΡΠ½Π°Ρ |
| Π£ΠΏΠ°ΠΊΠΎΠ²ΠΊΠ° | Π Π°Π·ΡΠ΅Π·Π½Π°Ρ ΠΠ΅Π½ΡΠ° |
| Π£ΡΠΎΠ²Π΅Π½Ρ Π§ΡΠ²ΡΡΠ²ΠΈΡΠ΅Π»ΡΠ½ΠΎΡΡΠΈ ΠΊ ΠΠ»Π°ΠΆΠ½ΠΎΡΡΠΈ (MSL) | MSL 1 - ΠΠ΅Π·Π»ΠΈΠΌΠΈΡΠ½ΡΠΉ |