
- ΠΠ°Π»ΠΈΡΠΈΠ΅: ΠΠΎΠ΄ Π·Π°ΠΊΠ°Π· 3-4 Π½Π΅Π΄Π΅Π»ΠΈ
LOGIC, 4BIT UP/DOWN COUNTER, 16DIP.
The SN74LS193N is a synchronous 4-bit up/down Binary Counter with dual clock and clear. This monolithic circuit is synchronous reversible counter having a complexity of 55 equivalent gates. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincidently with each other when so instructed by the steering logic. This mode of operation eliminates the output counting spikes which are normally associated with asynchronous counter. The outputs of the four master-slave flip-flops are triggered by a low-to-high-level transition of either count input. The direction of counting is determined by which count input is pulsed while the other count input is high. A clear input has been provided which forces all outputs to the low level when a high level is applied. The clear function is independent of the count and load inputs. The clear, count and load inputs are buffered to lower the drive requirements.
Π₯Π°ΡΠ°ΠΊΡΠ΅ΡΠΈΡΡΠΈΠΊΠΈ | |
SVHC (ΠΡΠΎΠ±ΠΎ ΠΠΏΠ°ΡΠ½ΡΠ΅ ΠΠ΅ΡΠ΅ΡΡΠ²Π°) | No SVHC (15-Jun-2015) |
ΠΠΎΠ»ΠΈΡΠ΅ΡΡΠ²ΠΎ ΠΡΠ²ΠΎΠ΄ΠΎΠ² | 16Π²ΡΠ²ΠΎΠ΄(-ΠΎΠ²) |
ΠΠ°ΠΊΡΠΈΠΌΠ°Π»ΡΠ½Π°Ρ Π Π°Π±ΠΎΡΠ°Ρ Π’Π΅ΠΌΠΏΠ΅ΡΠ°ΡΡΡΠ° | 70Β°C |
ΠΠ°ΠΊΡΠΈΠΌΠ°Π»ΡΠ½ΠΎΠ΅ ΠΠ°ΠΏΡΡΠΆΠ΅Π½ΠΈΠ΅ ΠΠΈΡΠ°Π½ΠΈΡ | 5.25Π |
ΠΠ°ΠΊΡΠΈΠΌΠ°Π»ΡΠ½ΡΠΉ Π‘ΡΠ΅Ρ | 16 |
ΠΠΈΠ½ΠΈΠΌΠ°Π»ΡΠ½Π°Ρ Π Π°Π±ΠΎΡΠ°Ρ Π’Π΅ΠΌΠΏΠ΅ΡΠ°ΡΡΡΠ° | 0Β°C |
ΠΠΈΠ½ΠΈΠΌΠ°Π»ΡΠ½ΠΎΠ΅ ΠΠ°ΠΏΡΡΠΆΠ΅Π½ΠΈΠ΅ ΠΠΈΡΠ°Π½ΠΈΡ | 4.75Π |
Π‘ΡΠΈΠ»Ρ ΠΠΎΡΠΏΡΡΠ° ΠΠΈΠΊΡΠΎΡΡ Π΅ΠΌΡ ΠΠΎΠ³ΠΈΠΊΠΈ | DIP |
Π’Π°ΠΊΡΠΎΠ²Π°Ρ Π§Π°ΡΡΠΎΡΠ° | 32ΠΠΡ |
Π’ΠΈΠΏ Π‘ΡΠ΅ΡΡΠΈΠΊΠ° | ΠΠ²ΠΎΠΈΡΠ½ΡΠΉ, Π‘ΠΈΠ½Ρ ΡΠΎΠ½Π½ΡΠΉ, ΠΠ²Π΅ΡΡ / ΠΠ½ΠΈΠ· |
Π£ΠΏΠ°ΠΊΠΎΠ²ΠΊΠ° | ΠΠΎΡΡΡΡΠ½ΠΎ |
Π£ΡΠΎΠ²Π΅Π½Ρ Π§ΡΠ²ΡΡΠ²ΠΈΡΠ΅Π»ΡΠ½ΠΎΡΡΠΈ ΠΊ ΠΠ»Π°ΠΆΠ½ΠΎΡΡΠΈ (MSL) | - |