SN74LV165ADR

Регистр сдвига, семейство LV, Параллельный в Последовательный, Последовательный в Последовательный.

The SN74LV165ADR is a 8-bit parallel-load Shift Register designed for 2 to 5.5V VCC operation. When it is clocked, data is shifted toward the serial output QH. parallel-in access to each stage is provided by eight individual direct data inputs that are enabled by a low level at the shift/load (SH/LD) input. It features a clock-inhibit function and a complemented serial output, QH. clocking is accomplished by a low-to-high transition of the clock (CLK) input while SH/LD\ is held high and clock inhibit (CLK INH) is held low. The functions of CLK and CLK INH are interchangeable. Since a low CLK and a low-to-high transition of CLK INH accomplishes clocking, CLK INH should be changed to the high level only while CLK is high. parallel loading is inhibited when SH/LD\ is held high. The parallel inputs to the register are enabled while SH/LD\ is held low, independently of the levels of CLK, CLK INH or SER.